The present invention relates generally to a semiconductor device and method of manufacturing the same and, more specifically, to a structure and method for manufacturing a semiconductor device with a low-k spacer.
As semiconductor device dimensions aggressively shrink, the adverse impact of parasitics such as gate-to-contact parasitic capacitance and fringing capacitance on device performance becomes more and more severe, particularly for semiconductor devices with a raised source/drain (RSD) such as an extremely thin silicon on insulator (ETSOI), FinFET or nanowire device. An ETSOI, FinFET or nanowire device requires a RSD to lower source/drain (S/D) resistance. Reducing parasitic capacitance is critical for improving AC performance while maintaining low power.